Details of Grant 

EPSRC Reference:	EP/C005686/1
Title:	ReSIP - Reconfigurable System-on-Chip based Networks of Integrated and Distributed Sensor Platform Nodes for Environmental Diagnostic and Sensing
Principal Investigator:	McDonald-Maier, Professor K
Other Investigators:
Researcher Co-Investigators:
Project Partners:	ClearSpeed Technology Epson (UK) Ltd
Department:	Computer Sci and Electronic Engineering
Organisation:	University of Essex
Scheme:	Standard Research (Pre-FEC)
Starts:	01 October 2005	Ends:	30 September 2008	Value (£):	265,844
EPSRC Research Topic Classifications:	System on Chip
EPSRC Industrial Sector Classifications:	Electronics
Related Grants:	EP/C51503X/1
Panel History:
Summary on Grant Application Form
Technology advances have made it possible to deploy ad-hoc and flexible networks with some small network elements, called PicoNodes, also referred to sometimes as networks of integrated and distributed sensor platform nodes (ISPDN). These nodes are associated with restricted constraints such as to: be smaller than one cubic centimetre, weigh less than 100 grams, have ultra-low power consumption and low cost. Typically a network with hundreds of these devices will be used in each application. Potential uses of such devices are unlimited; example applications of these networks are microclimate control in buildings, environmental monitoring, home automation, interactive museums, personalization and more.The task of replacing batteries on up to thousands of PicoNodes is impractical. For this reason it is crucial to identify methods of effectively managing power consumption at different levels of the network design. This could range from network routing down to the architecture of individual nodes. Efficient methods of networking a large number of energy-constrained nodes is a challenging problem that has recently been the focus of many researchers. Furthermore, the design and verification of these highly-complex devices also present a significant problem for designers. For this reasons, there is a continuous need to increase the flexibility, programmability and debug support of these devices without sacrificing speed and power performance. This increases the importance of reconfigurability since these nodes will be deployed in a wide range of applications, and hence they will need to adapt to their environment. Example issues are: as the energy goes down, it may be preferable to have lower quality of data to make the nodes last longer. Another issue is using the same hardware platform to adapt to different conditions where these nodes are planted. For example, variation in temperature or Ph might lead to change in the dynamic range of values processed by the node's computational unit and hence the number of resources or computational blocks and their associated interconnect could be disabled resulting in power savings. On the other hand if the node is located in a changed environment where different sensing devices are required, then the architecture can be reconfigured to suit the needs of such an environment.The dynamic multiple functionality aspect combined with the area and power requirement of such devices make a custom reconfigurable System-on-Chip (SoC) implementation the obvious approach to follow. For such SoC based hardware architectures to be developed and operate, effective development support is essential. Novel sensor nodes such as the proposed create further debugging challenges as each type of node is likely to contain a number of diverse dynamically reconfigurable that are interconnected using reconfigurable hierarchical bus structures. In addition these sensor nodes can be connected using a variety of fixed or wireless communication links. Dynamically reconfigurable systems introduce a new problem concept for debug support as, unlike conventional SoCs, their underlying hardware is no longer static, making debugging only feasible through system centric support that incorporates on-chip infrastructure. In addition, effective power management requires adaptive management algorithms combined with suitable configurability to support their specific applications but remain sufficiently generic to operate across a range of sensor nodes architectures. The aim of this research is to develop a novel reconfigurable SoC platform for ISPDN applications. This platform will provide a comprehensible solution which tackles both architectural issues which require ultra low power consumption and dynamic on site reconfiguration. It will investigate new algorithms to allow developers to overcome the challenges of distributed and dynamically reconfigurable architectures.
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Organisation Website:	http://www.sx.ac.uk