| EPSRC Reference: |
EP/C007298/1 |
| Title: |
Synchronizer Reliability in the Next Generation of SoC with Multiple Clocks |
| Principal Investigator: |
Yakovlev, Professor A |
| Other Investigators: |
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| Researcher Co-Investigators: |
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| Project Partners: |
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| Department: |
Electrical, Electronic & Computer Eng |
| Organisation: |
Newcastle University |
| Scheme: |
Standard Research (Pre-FEC) |
| Starts: |
01 July 2005 |
Ends: |
30 September 2008 |
Value (£): |
219,200
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Summary on Grant Application Form |
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As the size of systems on chip (SoC) has increased, it has become difficult or impossible to accurately distribute a single global clock across the entire system. Future systems are likely therefore to consist of many independently, or semi-independently clocked regions, with a need for synchronization of the data passing between them. Consequently there will be many more synchronizers whose performance and reliability is crucial to the performance of the system itself. Current synchronizers are untested at the levels of reliability required, and the increasing process fluctuations resulting from smaller dimensions are likely to worsen their relative performance. This three-year proposal aims to develop measurement techniques to validate synchronizer circuits at the reliability levels required, and to develop more robust circuits which will deliver the performance necessary for future multi-billion-transistor SoC.
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Key Findings |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Potential use in non-academic contexts |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Impacts |
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| Description |
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk |
| Summary |
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| Date Materialised |
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Sectors submitted by the Researcher |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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| Project URL: |
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| Further Information: |
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| Organisation Website: |
http://www.ncl.ac.uk |