Details of Grant 

EPSRC Reference:	EP/C508793/1
Title:	Stress-Induced Leakage Current (SILC) in Thin Gate Oxides of MOSFETs
Principal Investigator:	Zhang, Professor W
Other Investigators:
Researcher Co-Investigators:
Project Partners:
Department:	Sch of Design Engineering and Computing
Organisation:	Bournemouth University
Scheme:	First Grant Scheme Pre-FEC
Starts:	21 March 2005	Ends:	30 September 2005	Value (£):	123,373
EPSRC Research Topic Classifications:	Electronic Devices & Subsys.
EPSRC Industrial Sector Classifications:	Electronics
Related Grants:
Panel History:
Summary on Grant Application Form
The feature size of Metal-Oxide-Semiconductor (MOS) transistors, which is the most important active element in integrated circuit (IC) technology, has kept scaling down aggressively in recent years. The thickness of its gate oxide is one of the key parameters rapidly approaching its fundamental limit, resulting in serious concerns about its reliability and lifetime prediction. The Stress-Induced Leakage Current (SILO) has been used to characterise the degradation of ultra-thin gate oxides and to predict their breakdown and lifetime, as it is generally believed that SILO is caused by defects generated in gate oxides. However, the mechanism of the SILO is still not clear, since much less attention has been paid to investigating the relation between the SILO and defect generation in the oxide, especially how the defect can act as a step-stone for the SILO. The latest results from IBM suggested that the SILO measurements might not be used as a reliable measure of the critical defect density. The applicant's recent results also indicate a complicated relation between the generated defects and the SILO. The objective of this research is to carry out an in-depth investigation on the SILO generation and its relation with defect generation, and to assess its impact on the oxide breakdown prediction. This will provide important information to the quality assessment, reliability and modeling sections of the IC industry. The most important outcome of this research will be the potential improvement in the IC reliability assessment techniques.
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