Details of Grant 

EPSRC Reference:	EP/C528328/1
Title:	SOCCAD: Automatic Generation of New Hybrid SoC Architectures for Low Power High Performance Applications
Principal Investigator:	Arslan, Professor T
Other Investigators:	Beaumont, Professor S Erdogan, Dr AT
Researcher Co-Investigators:
Project Partners:	Epson (UK) Ltd Institute for System Level Integration Spiral Gateway Ltd
Department:	Sch of Engineering
Organisation:	University of Edinburgh
Scheme:	Standard Research (Pre-FEC)
Starts:	01 November 2005	Ends:	30 April 2009	Value (£):	260,512
EPSRC Research Topic Classifications:	System on Chip VLSI Design
EPSRC Industrial Sector Classifications:	Electronics
Related Grants:
Panel History:
Summary on Grant Application Form
This is an adventurous proposal which is inspired by the success of IP core-based approaches in order to develop an ambitious environment supporting single step automatic synthesis of new SoC architectures, which incorporate high performance reconfigurable IP cores as well as hybrid interconnection schemes which are not used in current conventional SoC designs, targeting low power high performance applications. Such SoC architectures we term in this proposal as hybrid SoCs. The research will be based on the configure-and-execute approach, in which the designer starts with a pre-designed SoC platform, and then configures that platform (including adding and deleting some components) before generating a new silicon. However, the configure-and-execute approach, as it stands, is restrictive, not generic and not able to cope efficiently with the large number of parameters, associated with complex SoCs specially those incorporating reconfigurable IP cores and hybrid interconnection networks. For this reason, this proposal aims to develop C/C++ based system-level simulation and power consumption models for each SoC component and develop algorithms to explore the vast number of configurations in a rapid and efficient manner. The exploration will begin with an initial SoC platform which will be subjected to platform transformations and parameter optimisations, creating many configurations. This stage will then be followed by identifying the efficiency of each configuration using C/C++ system-level simulation and power consumption models for rapid simulation and evaluation. The best solution for a given application and set of constraints will be identified and produced as a synthesisable RTL for the complete SoC system.
Key Findings
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Potential use in non-academic contexts
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Organisation Website:	http://www.ed.ac.uk