Details of Grant

EPSRC Reference:

EP/E003125/1

Title:

Meeting the design challenges of the nano-CMOS electronics

Principal Investigator:

Asenov, Professor A

Other Investigators:

Roy, Professor S

Sinnott, Professor R

Cumming, Professor DRS

Researcher Co-Investigators:

Project Partners:

A R M Ltd	Freescale Semiconductor	Fujitsu
Synopsys (International)	Wolfson Microelectronics

Department:

Electronics and Electrical Engineering

Organisation:

University of Glasgow

Scheme:

Standard Research

Starts:

01 October 2006

Ends:

31 January 2011

Value (£):

1,955,965

EPSRC Research Topic Classifications:

Electronic Devices & Subsys.	Information & Knowledge Mgmt
System on Chip

EPSRC Industrial Sector Classifications:

Electronics

Related Grants:

Panel History:

Summary on Grant Application Form

The years of 'happy scaling' are over and the fundamental challenges that the semiconductor industry faces, at both technology and device level, will impinge deeply upon the design of future integrated circuits and systems. This proposal brings together semiconductor device, circuit and system experts from academia and industry and e-scientists with strong grid expertise. Only by working in close collaboration, and adequately connected and resourced by e-science and Grid technology, can we understand and tackle the design complexity of nano-CMOS electronics, securing a competitive advantage for the UK electronics industry.Increasing variability in device characteristics and the need to introduce novel device architectures represent major challenges to scaling and integration for present and next generation nano-CMOS transistors and circuits. This will in turn demand revolutionary changes in the way in which future integrated circuits and systems are designed. Strong links must be established between circuit design, system design and fundamental device technology to allow circuits and systems to accommodate the individual behaviour of every transistor on a chip. Design paradigms must change to accommodate this increasing variability. Adjusting for new device architectures and device variability will add significant complexity to the design process, requiring orchestration of a broad spectrum of design tools by geographically distributed teams of device experts, circuit and system designers. This can only be achieved by embedding e-science technology and know-how across the whole nano-CMOS electronics design process and revolutionising the way in which these disparate groups currently work.This project's over-arching aim is to revolutionise existing nano-CMOS electronics research processes by developing the methodology and prototype technology of a nano-CMOS Design Grid. We use the term Grid to encompass computing technologies that allow distributed groups to collaborate by sharing designs, simulations, workflows, data sets and computation resources. This work will require a deep understanding of how electronics scientists, engineers and designers can work together to produce new methods and results. Through this process we will create Grid-savvy nano-CMOS e-Researchers able to Grid-enable their own simulations, to correctly annotate their own data, to design workflows reflecting their design processes, and share all these with other researchers in the nano-CMOS design space.

Key Findings

This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk

Potential use in non-academic contexts

This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk

Impacts

Description	This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
Summary
Date Materialised

Sectors submitted by the Researcher

This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk

Project URL:

Further Information:

Organisation Website:

http://www.gla.ac.uk