| EPSRC Reference: |
EP/E023150/1 |
| Title: |
Novel nano-scale Screen-grid FET technology for ultra low power applications |
| Principal Investigator: |
Fobelets, Dr K |
| Other Investigators: |
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| Department: |
Electrical and Electronic Engineering |
| Organisation: |
Imperial College London |
| Scheme: |
Standard Research |
| Starts: |
01 December 2006 |
Ends: |
30 November 2009 |
Value (£): |
144,472
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| EPSRC Research Topic Classifications: |
| Electronic Devices & Subsys. |
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Summary on Grant Application Form |
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A novel planar Field Effect Transistor (FET) has been proposed with a 3D gating configuration that allows to minimise the deterioration of the characteristics of the FET when downscaling, a problem that hinders current FET technology. The FET is defined on Silicon on insulator (SOI) and is called Screen-Grid FET (SGFET) because of its analogy with tetrodes in vacuum tube technology.In this research we will first establish the operation parameters of the SGFET and investigate the influence of downscaling on both DC and AC characteristics. This will be done via the use of commercially available TCAD models such as Medici and Taurus (from Synopsis).In the second stage we will compare the operation of the novel SGFET with current FET technology such as fully-depleted FETs on SOI (FDSOI) and the finFET, also defined on SOI. This comparison, both for analog and digital applications, will be based on precisely defined benchmarking parameters.Finally we will evaluate critically the impact of the chosen mobility models on the operation of the devices. This will be done by introducing Monte Carlo generated mobility models into the TCAD environment that will enable a better electric field dependency of the carrier mobility in the 3D stucture.The result of this TCAD modelling will establish if the proposed 3D planar SGFET on SOI is a competitor for current novel FET structures structures such as finFETs and FDSOI MOSFETs. It will also establish the application domains in which the SGFET might outperform the current novel hightech devices. These domains can be analog and/or digital and low and/or full power applications.A positive outcome of the benchmarking exercise will prolong the lifetime of CMOS technology by 1) relaxing the need for agressive downscaling and 2) by disconnecting the geometry involved in downscaling from the parameters that lead to the deterioration of the device operation.
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Key Findings |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Potential use in non-academic contexts |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Impacts |
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| Description |
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk |
| Summary |
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| Date Materialised |
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Sectors submitted by the Researcher |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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| Project URL: |
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| Further Information: |
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| Organisation Website: |
http://www.imperial.ac.uk |