| EPSRC Reference: |
EP/E062164/1 |
| Title: |
Energy Efficient Networks-on-Chip for Dynamically Reconfigurable Computing Platforms. |
| Principal Investigator: |
Nunez-Yanez, Dr J |
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| Department: |
Electrical and Electronic Engineering |
| Organisation: |
University of Bristol |
| Scheme: |
Standard Research |
| Starts: |
12 December 2007 |
Ends: |
11 December 2010 |
Value (£): |
282,919
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Summary on Grant Application Form |
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The purpose of this work is to investigate an on-chip network fabric that will enable future reconfigurable computing systems integrating tens or hundreds of processing tiles implementing embedded microprocessors, intellectual property cores, reconfigurable fabrics, dedicated local memories and DSP functionality. The reconfigurable NoC fabric will direct the effective communication and exchange of data among the multiple processing tiles and enable fault-tolerance and very high communication bandwidths with low-latency and low energy consumption. The processing tiles will morph their functionality and operation point based on the application demands.
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Key Findings |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Potential use in non-academic contexts |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Impacts |
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| Description |
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk |
| Summary |
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| Date Materialised |
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Sectors submitted by the Researcher |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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| Project URL: |
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| Further Information: |
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| Organisation Website: |
http://www.bris.ac.uk |