Details of Grant 

EPSRC Reference:	EP/G011052/1
Title:	The Reduceron: high level symbolic computing on FPGA
Principal Investigator:	Runciman, Professor C
Other Investigators:
Researcher Co-Investigators:
Project Partners:
Department:	Computer Science
Organisation:	University of York
Scheme:	Standard Research
Starts:	01 October 2008	Ends:	31 March 2010	Value (£):	100,364
EPSRC Research Topic Classifications:	Fundamentals of Computing System on Chip
EPSRC Industrial Sector Classifications:	No relevance to Underpinning Sectors
Related Grants:
Panel History:
Summary on Grant Application Form
Symbolic computing is a key technology with programs often written in very expressive high level languages. The Reduceron is a custom processor for executing such symbolic programs by a technique called graph reduction. It is built on an FPGA (Field-Programmable Gate Array), a medium that allows rapid exploration of alternative designs. The current prototype was developed in just 2--3 months as a case-study in the closing stages of a PhD. Early results are sufficiently promising that we propose a 15-month feasibility study researching the potential of a special-purpose processor based on an advanced Reduceron. Results will be immediately applicable in FPGA-based systems and could inform the future design of a SPU (Symbolic Processing Unit) analogous to current highly successful GPUs for graphics.
Key Findings
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Potential use in non-academic contexts
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Impacts
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Sectors submitted by the Researcher
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Project URL:	http://www.cs.york.ac.uk/fp/reduceron/
Further Information:
Organisation Website:	http://www.york.ac.uk