Details of Grant 

EPSRC Reference:	EP/H014608/1
Title:	Configurable Analogue Transistors: Conquering Unreliability in a Shrinking World
Principal Investigator:	Wilson, Professor P
Other Investigators:	Al-Hashimi, Professor B
Researcher Co-Investigators:
Project Partners:
Department:	Electronics and Computer Science
Organisation:	University of Southampton
Scheme:	Standard Research
Starts:	13 February 2010	Ends:	12 August 2013	Value (£):	442,062
EPSRC Research Topic Classifications:	Electronic Devices & Subsys. VLSI Design
EPSRC Industrial Sector Classifications:	No relevance to Underpinning Sectors
Related Grants:
Panel History:	Panel Date Panel Name Outcome 30 Sep 2009 ICT Prioritisation Panel (Oct 09) Announced
Summary on Grant Application Form
The development of silicon based semiconductor technology is heading towards increasingly smaller components with transistors being scaled down to nanometre dimensions. As an example, Intel are currently developing their 45 nm and 65 nm technologies, which are placed to overtake the current 90 nm and 130 nm processes used for most of their microprocessors. Europe is lagging behind the USA in these modern technologies, and it is desirable that European scientific excellence in the field of silicon based nano-device electronics is further strengthened. A particular area where UK researchers can make significant inroads is to investigate solutions to the problem of increasingly poor yield.As device dimensions shrink, digital circuit performance on the whole continues to thrive. The reality of multi-processors on a single die has been realized and the prospects for continued success beyond 65 nm are bright. Due to this extensive integration capability, the need has grown for AMS support circuitry, on what are predominantly digital chips. Integrating a wide range of analogue circuit functions on the same silicon as vast microprocessor and memory blocks brings about new challenges for analogue design. As a result, the analogue parts of system chips are now becoming a serious design bottleneck. Typically 10% of the chip design may be analogue in function, but this same section can absorb 90% of the design time. Now, more than ever, analogue designers realize they will become as reliant on design automation tools as the digital design community, especially with increasing pressure on time to market precluding the received wisdom of bespoke analogue design for every chip design and process node that emerges. We propose a novel approach that allows poor yield and performance to be improved post manufacture. The Configurable Addressable Transistor (CAT) concept allows an individual transistor within a design to be addressed, and its width adjusted. Replacement of a number of transistors in an analogue functional block with CAT devices allows adjustment of the block's overall characteristics to be achieved after its manufacture. This allows statistical performance spread due to process variations to be compensated for at the silicon test stage, leading to a significant improvement in a die's performance and therefore an improvement in overall yield. The elegance in the proposed approach is partly due to the flexibility of its implementation. This flexibility leads to clear tradeoffs which can be leveraged in order to maximise the improvement in yield for a particular application. There are three main trade-off points in the approach which include critical device identification, optimum CAT sizing and post-manufacture configuration.Critical device identificationA CAT device occupies more area than the transistor it replaces, so it is important to trade-off potential benefits with increased area overheads and complexity. The first stage is therefore to identify 'critical' transistors in the design, where variations in these devices are most likely cause the design to fail specification. Only a certain number of critical devices will be replaced with CAT devices, ensuring the best trade-off between overheads and yield improvement. Optimum CAT sizing and insertionHaving determined which transistors will be replaced with CAT devices, it is necessary to optimise each of these CAT replacements to achieve the best possible yield improvement in terms of the overall design. A key aspect of the application of the CAT approach will be the development of Electronic Design Automation (EDA) methodologies that will manage the process of automatically sizing and inserting the new CAT devicesPost manufacture configurationThe proposed approach is fundamentally different to conventional design techniques and this new research direction is essential to address the challenges emerging from the issue of shrinking technologies.
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