Details of Grant 

EPSRC Reference:	EP/H017119/1
Title:	Optimization of Massively Parallel Stochastic Simulations
Principal Investigator:	Bouganis, Dr CS
Other Investigators:
Researcher Co-Investigators:
Project Partners:
Department:	Electrical and Electronic Engineering
Organisation:	Imperial College London
Scheme:	First Grant - Revised 2009
Starts:	01 May 2010	Ends:	30 June 2011	Value (£):	98,308
EPSRC Research Topic Classifications:	VLSI Design
EPSRC Industrial Sector Classifications:	No relevance to Underpinning Sectors
Related Grants:
Panel History:	Panel Date Panel Name Outcome 02 Sep 2009 ICT Prioritisation Panel (Sept 09) Announced
Summary on Grant Application Form
Non-traditional architectures have shown massive energy savings and a significant boost on the performance of many applications across a range of domains. In order these high gains to be achieved, efficient use of silicon should be performed when such algorithms are mapped onto hardware. Even though this topic is well researched for the case of deterministic algorithms, no work has been done for algorithms of a stochastic nature. The fundamental problem that this proposal addresses is the efficiently use of silicon when a stochastic algorithm is mapped to hardware.This proposal is concerned with the design automation of hardware architectures for Monte Carlo based simulations of Stochastic Differential Equations (SDEs). Domains such as the stochastic modelling of chemical reactions and financial engineering are two examples where SDEs are widely used. Due to the non-existence or to high complexity in deriving an analytic solution for an SDE, numerical techniques based on computationally heavy Monte Carlo simulations are often employed. Hardware systems based on reconfigurable logic have demonstrated good potential for the acceleration and power consumption reduction of the above simulations. The main technique that is often employed and contributes to the realization of high performance gains and significant power consumption reduction is the use of a customized number representation system.This project aims to investigate two key issues related to the use Field Programmable Gate Arrays, a reconfigurable hardware device, for acceleration of Monte Carlo simulations for Stochastic Differential Equations. The first issue is the impact of the employed number representation on the quality of the SDE solution using Monte Carlo simulations, while the second key issue is to research and develop hardware architectures and word-length optimization techniques that target the minimization of power usage or the maximization of the performance of the system, without significant loss on the quality of the solution. By optimizing the computational part of the hardware system, efficient allocation of the available resources is performed, resulting in the acceleration of the overall simulation and improved energy consumption per computational operation.
Key Findings
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
Potential use in non-academic contexts
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
Impacts
Description This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk Summary Date Materialised
Sectors submitted by the Researcher
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
Project URL:
Further Information:
Organisation Website:	http://www.imperial.ac.uk