Details of Grant 

EPSRC Reference:	EP/I004084/1
Title:	Quantum Simulations of Future Solid State Transistors
Principal Investigator:	Martinez, Dr AE
Other Investigators:
Researcher Co-Investigators:
Project Partners:	Gold Standard Simulations Institute of Material Sciences Barcelona Swiss Federal Institute of TEC UCL Universites d'Aix-Marseille Paul Cezanne University of Southampton
Department:	Electronics and Electrical Engineering
Organisation:	University of Glasgow
Scheme:	Career Acceleration Fellowship
Starts:	01 October 2010	Ends:	18 July 2011	Value (£):	712,369
EPSRC Research Topic Classifications:	Electronic Devices & Subsys.
EPSRC Industrial Sector Classifications:	No relevance to Underpinning Sectors
Related Grants:
Panel History:	Panel Date Panel Name Outcome 09 Jun 2010 EPSRC Fellowships 2010 Interview Panel F Announced
Summary on Grant Application Form
Computers and electronic gadgets, such as the iphone, have transformed modern life. The silicon transistor is at the core of this revolution, having been continuously made faster and smaller over the last forty years. In a chip, millions of them are squeezed into an area the size of a pinhead, switching a billion times in one second. Transistor size has now reached nanometre dimensions; one nanometre is only ten time larger than an atom. Moore's law, which dictates that transistor size halves every two years and is the driving force behind the success of the electronics industry, has come to a halt. The happy and easy days of transistor scaling are now gone. Quantum mechanical laws conspire against transistor function making it leak when switched off and generating poor electrical control. Also, our inability to control the precise atomic structure of interfaces and chemical composition during fabrication makes transistors less predictable. Hence semiconductor companies are searching for alternative, non-planar (multigate) transistor architectures and novel devices such as nanowires, nanotubes, graphene and molecular transistors, which will ultimately break through the nano-size barrier resulting in a completely new era of miniaturization. There is a significant gap between our ability to fabricate transistors and to predict their behaviour.The simulation and prediction of the silicon transistor has become an vital mission. Current planar transistor architecture presents serious problems in scalability regarding leakage and controllability. Transistors of nanometre dimensions are more vulnerable to the atomic nature of matter than their previous cousins of micrometre dimensions. Furthermore, at nanoscales heat transfer is a source of heat death for novel transistor applications due to the decrease of thermal conductivity. Within this context I propose to develop a Quantum Device simulator, with atomic resolution that will enable the accurate prediction of present and future transistor performance. The simulator will deploy a quantum wave description of electron propagation, treating the interaction of electrons with crystal lattice vibrations (heat) at a fully quantum mechanical level. It will have the capability of describing the electron interactions with the roughness of the semiconductor/dielectric interface and with each other under the effect of a high electric field. Devices will be properly tested and optimised regarding materials, chemical composition and geometry without the high costs implicit in fabrication. A wide range of transistors will be explored from planar, non-planar and novel. This is timely as existing computer design tools lack predictive capabilities at the nanoscale and the industrial build-and-test approach has become prohibitively costly. Efficient quantum-models/algorithms/methodologies and tools will be developed.These are dynamic times as device dimensions move closer to the realm of atoms, which are inherently uncontrollable. In this regime two streams collide: the classical and quantum worlds making the need for new regularities and patterns vital as we strive to conquer nature at this scale. This offers exiting opportunities to merge an engineering top-to-bottom approach with a physics bottom-up approach. As 21st century environmental concerns rise, the need for greener technology is increasing. My proposal addresses the lowering of power consumption, raw material reductions delivering more functionality and the provision of a cheaper way to assess new design technologies. Collectively, these will help companies to provide a greener alternative to consumers.
Key Findings
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Organisation Website:	http://www.gla.ac.uk