| EPSRC Reference: |
EP/I005900/1 |
| Title: |
VARMA - Variability Modelling and Analysis Tool |
| Principal Investigator: |
Russell, Dr G |
| Other Investigators: |
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| Researcher Co-Investigators: |
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| Project Partners: |
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| Department: |
Electrical, Electronic & Computer Eng |
| Organisation: |
Newcastle University |
| Scheme: |
Follow on Fund |
| Starts: |
01 October 2010 |
Ends: |
31 December 2011 |
Value (£): |
117,777
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| EPSRC Research Topic Classifications: |
| System on Chip |
VLSI Design |
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| EPSRC Industrial Sector Classifications: |
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| Related Grants: |
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| Panel History: |
| Panel Date | Panel Name | Outcome |
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29 Apr 2010
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Follow On Fund 8
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Announced
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Summary on Grant Application Form |
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VARMA(Variability Modelling and Analysis) tool is under development as a user friendly tool which interfaces standard Process/Device simulators and Circuit simulators allowing the identification of process variations which will have most effect on device and circuit performance and their subsequent assimilation into circuit design stages. VARMA thus bridges the gap between design and technology. The rationale for its development is summarised below.To satisfy market demands, chip complexity is not only increasing from the aspect of the designer but also for fabrication. It is estimated that with current technologies the fabrication process requires in excess of 34 masks, 500 processing steps and over 600 hundred design rules, with an average, overall, design cost of $30M, with mask costs increasing by 50% with each advance to the next technology node. Furthermore, it is considered that for a new product the possibility for a re-spin is 50-80% introducing a 12-16 week delay in the product reaching the market place. Consequently first spin success is crucial in a market place where a product is considered to be old within a year and market profile over time looks more like an impulse function. However, it is considered that with sub 65nm technologies at least one design re-spin will be required before an acceptable manufacturing yield is obtained. In the past the main reasons for a design re-spin were functional design errors; although these have not been eliminated the major cause is now due to the effects of process variations. With the rapid changes in today's technologies, in order for products to compete in the market place, there are few opportunities to analyse the fabrication process to evolve a solution. Consequently, when there is a degree of uncertainty in the fabrication process the potential effects of fluctuations implicitly impact not only on the device manufacturability, yield and reliability but also on design 'aggressiveness' which affects device performance and subsequently the profitability of the product.As a result of both the complexity of present day design and the fabrication process, combating the effects of process variability can no longer be left to the semiconductor technologists to alleviate the problems by introducing a few 'tweaks' into the process as there are now too many variables to be considered. Consequently there is a need for a tool which bridges the gap between design and technology. The VARMA tool flow permits both the semiconductor technologist and designer to analyse the effects of process variations on device and circuit performance to improve the yield and also the optimisation of process parameters of manufactured devices so that their characteristics match the requirements of a given circuit application. Consequently, VARMA is being developed as a user friendly tool which interfaces standard Process/Device simulators and Circuit simulators.VARMA thus bridges the gap between design and technology with in-built user friendly tools for example, Process Wizard, technology library creator, cause and effect analyser etc., thus facilitating:a) The effects of process variability to be analysed.b) The optimisation of device and process parameters in order to achieve a given spread in circuit level performance characteristics.c) The automatic generation of technology libraries for Si, strained Si etc for a range of current and future processing nodes. VARMA differs form existing DFM tools in that it addresses variability issues related to their effects on the electrical behaviour of devices rather than on process steps which affect the design and physical implementation of the circuit.
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Key Findings |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Potential use in non-academic contexts |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Impacts |
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| Description |
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk |
| Summary |
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| Date Materialised |
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Sectors submitted by the Researcher |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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| Project URL: |
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| Further Information: |
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| Organisation Website: |
http://www.ncl.ac.uk |