Moore's Law, the observation that the number of components that can be placed on a silicon chip approximately doubles every two years, with commensurate increases in the processing and data storage capacities of devices, and decreases in the unit cost of components, has driven technological achievement and new materials science for 40 years. Devices featuring <45 nm feature sizes are now in production, and close-to-market chips with 22 nm feature sizes are being disclosed. However, to achieve these remarkable device sizes, top-down scaling is giving way to more complex and lithographically challenging 3-D designs, and conventional materials superseded. Although 'More Moore' remains an important driver for the semiconductor industry, the concept of 'More than Moore', in which added value is packaged into devices by adding functionalities that themselves do not necessarily scale in line with Moore's Law is growing as a design strategy. The integration of smaller and faster device technology with innovative total systems packaging is now seen as the most feasible route to improve device performance, recognising the increasing difficulties in following traditional top-down scaling. With or without More than Moore augmentation, if pace of electronic device development is to continue along a Moore's Law projection in the longer-term further reductions in feature size will be required. Two consequences flow from this proposition. The first is that, in the medium-long term, feature sizes will approach molecular dimensions. The second, more practical and more immediate consequence, is that new materials must now be integrated into silicon-based devices. In the present generation 45 nm chips , a SiO2 gate would be so thin as to leak too much current when the transistor is in the 'off' state. This problem was recognised, and the solution (a high-dielectric alternative insulator) apparent, long before the exact materials solution was conceived. HfO2 is now used as the transistor gate insulator despite the technical challenges inherent in depositing HfO2, a highly refractory and expensive material. Thus, while 'molecular electronics' is commonly perceived to be very difficult to implement, the continued development of 'traditional' silicon technology also faces profound and difficult challenges, which industry adapts to meet.
The term 'molecular electronics' is generally applied to structures designed to involve a single molecule, a small bundle of molecules, or a single layer of molecules, oriented between two contacts (which may be metals or semiconductors), with the critical dimension between the contacts therefore lying in the nanometer size range. Circuit components at the molecular level could exploit the small size of molecules and their enormous potential variation in structure and properties, controlled using the tools of synthetic chemistry, to increase device density and to incorporate new functionality into existing or new microelectronic architectures. Primary objectives in this research phase are (a) to identify classes of molecular materials, and their contacts, which display promising attributes for molecular electronics, (b) to identify and understand mechanisms by which the electrical properties can be exploited, (c) to further develop defined metrological techniques for reliably determining the electrical behaviour of molecular devices. To convey future practical relevance our focus will be on room temperature operation and condensed matter interfaces.
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