| EPSRC Reference: |
EP/L025507/1 |
| Title: |
A4A: Asynchronous design for analogue electronics |
| Principal Investigator: |
Yakovlev, Professor A |
| Other Investigators: |
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| Researcher Co-Investigators: |
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| Project Partners: |
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| Department: |
Sch of Engineering |
| Organisation: |
Newcastle University |
| Scheme: |
Standard Research |
| Starts: |
01 September 2014 |
Ends: |
31 January 2018 |
Value (£): |
574,524
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| EPSRC Research Topic Classifications: |
| Electronic Devices & Subsys. |
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| EPSRC Industrial Sector Classifications: |
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| Related Grants: |
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| Panel History: |
| Panel Date | Panel Name | Outcome |
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04 Feb 2014
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EPSRC ICT Responsive Mode - Feb 2014
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Announced
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Summary on Grant Application Form |
Succinctly, this research is about developing and applying asynchronous design methods, which were traditionally focused on digital systems, to the analogue world.
Power management ICs, for example, are becoming an area of rapid growth in research - the size, performance and energy requirements, as well as the overall holistic nature of modern ICT system engineering, call for a much more radical innovation in power converter and controller design than ever before. The overall market value for power management ICs had sales revenue of USD 16.9 billion in 2012 and is forecast to rise to USD 26 billion by 2018 (forecast CAGR ca. 7%), with total shipments of analogue devices forecast to jump 14% in 2013 - total sales revenue USD 41 billion). While errors in digital (data) paths are becoming less critical thanks to techniques such as approximate computing and smarter quality of service management, analogue blocks are becoming much more of a weakest link in new ICT systems.
The design of analogue circuits must be functionally correct to avoid catastrophic failures that would affect the entire system. Besides the functional correctness of design, the efficiency of analogue circuits, particularly of the power converters themselves, is a problem as they are becoming a significant energy drain, particularly when the data processing parts are idle.
The scope of this project is focused on the new design methods and tools that will support the digital electronics which is underneath the analogue circuits. In contrast with the data processing digital hardware ("big digital"), this layer of logic, responsible for controlling analogue blocks, can be named "little digital".
The issue of provable correctness is lagging far behind in the current practice of analogue engineering compared to digital systems. Analogue design with "little digital" is largely done by analogue engineers without any formal steps from the specification to netlists. No synthesis tools are available.
The project's main goal is to develop a new digital design methodology to be integrated in the process of developing predominantly analogue systems or subsystems of larger ICT systems. This methodology will use asynchronous design principles, specifications, modelling and associated tool support that would be able to address the following four main criteria:
1) Robustness of the digital and the whole hybrid system solution. This will enable building systems that are speed-independent, i.e. operate according to specifications (without glitches and hazards) in a wide dynamic range of PVT variations.
2) Clarity of specifications. The new model underpinning will eliminate the current practice of ad hoc design of the analogue systems with non-existent specification for digital control. Due to the continuous nature of analogue signals, the models for asynchronous logic like Signal Transition Graphs (STGs) will need to be modified and made suitable for the use by analogue designers.
3) Compositional design. The novel models based on Conditional Partial Order Graphs (CPOGs) will address the multitude of modes occurred in analogue circuits and enable specification, synthesis and verification of complex hybrid systems.
4) Automation is crucial. It will eliminate the current practice of manual design of hybrid circuits and days of simulation to validate their correctness. The new asynchronous for analogue (A4A) tools will radically improve design productivity of analogue engineers by introducing automated synthesis and formal verification flow.
These criteria will essentially mark our research path with the signposts of what is significant to our aims, and where we expect to achieve measurable outcomes. They have been corroborated by our main industrial partner Dialog Semiconductor, who are willing to use asynchronous design in developing their analogue IP solutions for applications in Mobile Systems, Wireless Connectivity, Automotive and Industrial sectors.
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Key Findings |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Potential use in non-academic contexts |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Impacts |
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| Description |
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk |
| Summary |
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| Date Materialised |
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Sectors submitted by the Researcher |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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| Project URL: |
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| Further Information: |
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| Organisation Website: |
http://www.ncl.ac.uk |