| EPSRC Reference: |
GR/A00027/01 |
| Title: |
AF: THE NEW GENERATION OF HIGH VOLTAGE POWER DEVICES |
| Principal Investigator: |
Udrea, Professor F |
| Other Investigators: |
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| Researcher Co-Investigators: |
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| Project Partners: |
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| Department: |
Engineering |
| Organisation: |
University of Cambridge |
| Scheme: |
Advanced Fellowship (Pre-FEC) |
| Starts: |
01 April 2000 |
Ends: |
31 July 2003 |
Value (£): |
104,031
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| EPSRC Research Topic Classifications: |
| Electronic Devices & Subsys. |
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Summary on Grant Application Form |
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The proposed project aims at developing novel power device structures for high voltage applications. This project challenges the state-of-the-art DMOS and JunctionIsolation (JI) technologies for discrete devices and power integrated circuits and proposes the next generation of power semiconductor devices based on trench and Silicon-on-Insulator (SOI) technologies. Novel fundamental physical concepts are employed to advance the performance of MOS-gate control into the area of ultra-high voltages (e.g. 6KV). These concepts are based on the MOS inversion or accumulation layers acting as virtual emitters in high power bipolar transistors or thyristors.The next generation of power semiconductor devices will offer crucial advantages over the existing generation, such as lower on-state resistance, higher frequency range, lower leakage currents and higher breakdown and current capabilities. The next generation is seen to be comprised of:1. Power Integrated Circuits (PICs) based on lateral integration for up to 1.5 KV. The PICs will be made in ultra thin SOI or partial SOI technology [1-3] with several power device cells integrated with CMOS low-voltage circuits.2. Intelligent hybrid power modules from 600 V to 6 KV comprised of highly advanced vertical power devices assembled in the same module with protection, driving and processing circuits. The vertical devices will be based on trench technology and may use the inversion layer or accumulation layer injection concept [4,5].3. The 2nd revolution of Power Integrated Circuits with vertical-lateral integration (at the very beginning of next century). Trench vertical devices integrated in the same chip with low-voltage CMOS circuits using partial SOI isolation technology.
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Key Findings |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Potential use in non-academic contexts |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Impacts |
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| Description |
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk |
| Summary |
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| Date Materialised |
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Sectors submitted by the Researcher |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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| Project URL: |
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| Further Information: |
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| Organisation Website: |
http://www.cam.ac.uk |