| EPSRC Reference: |
GR/H51750/01 |
| Title: |
HIGH LEVEL SYNTHESIS |
| Principal Investigator: |
Currie, Mr A |
| Other Investigators: |
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| Researcher Co-Investigators: |
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| Project Partners: |
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| Department: |
Electronics and Computer Science |
| Organisation: |
University of Southampton |
| Scheme: |
Standard Research (Pre-FEC) |
| Starts: |
01 October 1992 |
Ends: |
30 September 1995 |
Value (£): |
97,604
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| EPSRC Research Topic Classifications: |
| Design & Testing Technology |
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Summary on Grant Application Form |
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This project continues the development of the MOODS behavioural synthesis system which started under SERC grant GR/F73717. The objectives are the extension of the MOODS system into a VHDL environment; improvement of the algorithms, data structures and optimisation strategies used by the synthesis system; and enhancement of the usability of behavioural synthesis in the real world, primarily by automatically generating appropriate built-in test structures to ensure an acceptable degree of testability of the synthesised circuits.A subset of VHDL suitable for behavioural synthesis has been identified, and a compiler produced which translates this into the intermediate level ICODE representation used by the MOODS system. A library of high-level VHDL cells suitable for use in the synthesis process has been written. Output of the synthesised circuit from MOODS is now in the form of structural VHDL, suitable for direct input to TransGATE, a logic synthesis product developed by TransEDA Ltd. which serves as the back end of the behavioural synthesis system.A thorough performance analysis of the MOODS system has been conducted leading to some relatively minor changes which have nonetheless resulted in the reduction of execution times by up to 70% in some cases. A side effect of this analysis has been the discovery of a number of hitherto unknown bugs in the MOODS system; these have now been fixed. More major revision of the internal data structures and algorithms is planned; this work is ongoing at the time of writing. The most important aspect of the project is the incorporation of testability into synthesised circuits. This is based on a partial scan-path approach, where the test vectors for the design are generated using pre-computed test vectors for the modules used in the design. Test vectors for each module are generated by TransEDAs TransTEST tool and take into account immediate connectivity outside the module. Controllability and observability of the module test vectors from the primary inputs and outputs is achieved using transfer information for each module type in order to justify and propagate the appropriate vectors. This includes propagation of signals through the controller equations to the controller as well as through the data path. Work currently in progress focusses on improving the efficiency of the synthesis process by improvements to the optimisation strategy. It is intended to investigate the use of tailored heuristics based on speed and chip area as an alternative to the more general simulated annealing approach currently in use.
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Key Findings |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Potential use in non-academic contexts |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Impacts |
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| Description |
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk |
| Summary |
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| Date Materialised |
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Sectors submitted by the Researcher |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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| Project URL: |
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| Further Information: |
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| Organisation Website: |
http://www.soton.ac.uk |