| EPSRC Reference: |
GR/H51798/01 |
| Title: |
DESIGN AND OPTIMISATION OF MIXED SIGNAL MULTIRATE CIRCUITS |
| Principal Investigator: |
Sewell, Professor J |
| Other Investigators: |
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| Researcher Co-Investigators: |
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| Project Partners: |
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| Department: |
Electronics and Electrical Engineering |
| Organisation: |
University of Glasgow |
| Scheme: |
Standard Research (Pre-FEC) |
| Starts: |
01 September 1992 |
Ends: |
31 December 1995 |
Value (£): |
94,533
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| EPSRC Research Topic Classifications: |
| Design & Testing Technology |
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Summary on Grant Application Form |
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The project is concerned with the development of an integrated software suite for the analysis, design, optimisation and testing of mixed analogue/digital multirate circuits. This will require the development of software for complete front-end and back-end signal processing circuitry which is completely independent of fabrication technology and hardware platform. Progress:The work forms part of a larger project with the same title (ITD2/475/30/07) funded by the DT1/EPSRC VLSI Design Automation Advanced Technology programme, it involves the University of Glasgow and Wolfson Microelectronics Ltd, Edinburgh as partners. The overall original objectives cited above are still valid, though the Level II Plan has been modified (with mutual agreement of the Partners, DTI and Monitor) to accommodate the technological changes within the company. Original work by the University of Glasgow on the development of a behavioural simulator for over-sampled converter architectures has been absorbed into the company programme and refined to satisfy routine application by many users. It has been employed in the development of sophisticated high order delta-sigma converters. The University of Glasgow has developed a new, highly efficient switched network simulator, SCNAP4, capable of high speed noise analysis and non-ideal sensitivity analysis of multirate SC and SI filter systems. We also have been able to produce filter synthesis software capable of addressing the multirate environment in both SC and SI architectures. Optimisation facilities have been demonstrated to be very effective when applied to general SC, SI and continuous-time (active-RC and transconductance-C) filter systems. Close links have developed with another VLSI Design Automation Project-SCADS (University of Southampton, Philips Semiconductors Ltd, Philips Research Laboratory and Cadence UK) and software developed at the University of Glasgow is now integral to that project. Negotiations regarding exploitation of the software is at an advanced stage with two UK companies. In the remaining 7 months there is some technical work to complete, together with thorough evaluation and documentation of the software.
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Key Findings |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Potential use in non-academic contexts |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Impacts |
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| Description |
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk |
| Summary |
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| Date Materialised |
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Sectors submitted by the Researcher |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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| Project URL: |
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| Further Information: |
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| Organisation Website: |
http://www.gla.ac.uk |