| EPSRC Reference: |
GR/H73493/01 |
| Title: |
TECHNOLOGY INDEPENDENT COMPILATION OF ANALOGUE VLSI CIRCUITS |
| Principal Investigator: |
Walczowski, Dr L |
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| Department: |
Sch of Engineering & Digital Arts |
| Organisation: |
University of Kent |
| Scheme: |
Standard Research (Pre-FEC) |
| Starts: |
01 January 1993 |
Ends: |
31 May 1996 |
Value (£): |
171,888
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| EPSRC Research Topic Classifications: |
| Design & Testing Technology |
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Summary on Grant Application Form |
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The development of a circuit compiler environment to support the automatic design of analogue VLSI devices in a technology independent manner. For a given specification, the compiler will, for the chosen technology, produce a circuit design and layout to satisfy the required aims.Progress:The Circuit Specification Language (CSL) has been updated to use the facilities offered by the latest generation of C++ compilers. It has also been enhanced to support dynamic and multilevel domain inheritance of unlimited depth.Device-level models, suitable for circuit synthesis, have been developed for CMOS, Bipolar and BiCMOS technologies. In the CMOS domain, an operational amplifier synthesis program has been developed in CSL. For a wide range of specifications and processes, the matching between specification and simulation results is better than 2%, across all major specification parameters.In the Bipolar domain, sizing and modelling have been investigated and a sizing strategy for bipolar amplifiers has been produced. A prototype bipolar synthesis system has been produced.Based on the experience gained in CMOS and Bipolar domains, work is currently progressing towards the development of a BiCMOS synthesis tool in CSL. For the layout synthesis of these circuits, various approaches have been investigated. An expert system approach, based on symbolic floor plans is being developed. Layout generators for the basic, low-level building blocks have been produced. Working with the results obtained from the sizing software, the complete synthesis system uses the symbolic floor plan to generate and then place, the required low-level blocks. Currently work is progressing towards a symbolic router for interconnection of the analogue layout.
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Key Findings |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Potential use in non-academic contexts |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Impacts |
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| Description |
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk |
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Sectors submitted by the Researcher |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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| Project URL: |
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| Further Information: |
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| Organisation Website: |
http://www.kent.ac.uk |