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Logic Caching is a novel method of digital system synthesis which exploits the dynamic reconfiguration of certain FPGAs and the redundancy inherent in many digital systems, by allocating the resources of the FPGA only to those parts of the system which are currently active. As the activity profile of the system changes, the array is dynamically reconfigured to adapt, by loading newly-activated tasks in place of tasks which are no longer active. The inactive tasks are stored in external memory. Logic Caching offers the digital systems designer important benefits such as reduced cost, lower parts count and lower power consumption. The objectives of the project are to investigate the feasibility of Logic Caching and to examine the significance of dynamic reconfiguration in FPGA-based design.Progress:To date the research programme has progressed well and all the original targets have been met within the projected timescales. The progress may be summarised as follows: An initial survey of dynamically reconfigurable FPGAs to assess which of the available architectures is most suited to the evaluation of synthesis techniques based on Logic Caching resulted in selection of the Atmel 6000 series devices. The survey considered both hardware and CAD software issues. A universal hardware development system for investigating and prototyping applications of Logic Caching has been designed and constructed. It has been in continuous use for approximately a year now and a revision of the system, incorporating improvements resulting from the experience gained with the first system, is in progress. An investigation of simulation strategies for modelling dynamically reconfigurable systems has been conducted. The principal outcome has been the development of a new simulation method called dynamic circuit switching using virtual VHDL components to model the interaction between the logic and reconfiguration planes of dynamically reconfigurable FPGAs.. The technique integrates with existing FPGA design tools and enables quantitative performance analysis of Logic Caching circuits. A fully automated, netlist post-processing tool which implements dynamic circuit switching is currently nearing completion. Research into suitable application areas for dynamic reconfiguration has yielded promising results. Initial work included an evaluation of a reconfigurable Artificial Neural Network but this has been superseded by a more promising application area that has considerably wider impact. It is a testing strategy for FPGA-based designs that exploits dynamic reconfiguration to provide an alternative to current strategies employing dedicated self-test circuitry. Work in this area is ongoing. Several enhancements to existing FPGA architectures which provide greater design support and increased system performance for dynamic reconfiguration have been proposed. The simulation tool, once complete, will be used in the evaluation of some of these enhancements such as alternative high speed FPGA reconfiguration mechanisms.To date, the publication of four papers have been influenced by the availability of the grant: P. Lysaght and J. Dunlop, Dynamic Reconfiguration of Field Programmable Gate Arrays, More FPGAs, Abingdon, Oxford, UK, 1993. P. Lysaght, D. McConnell and H. Dick, Design Experience with Fine Grained FPGAs, Field Programmable Logic, Springer Verlag, Germany, 1994. P. Lysaght, J. Stockwood, J. Law and D. Girma, Artificial Neural Network Implementation on a Fine Grained FPGA, Field-Programmable Logic, Springer Verlag, Germany, 1994. P. Lysaght and H. Dick, Implementation of Adaptive Signal Processing Architectures based on Dynamically Reconfigurable FPGAs, EUSIPCO, Edinburgh, UK, Sept 1994.
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