| EPSRC Reference: |
GR/H76531/01 |
| Title: |
PHYSICS OF NOVEL STRUCTURES FOR APPLICATIONIN SUB-0 1 M IC PROCESSES |
| Principal Investigator: |
Ashburn, Professor P |
| Other Investigators: |
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| Researcher Co-Investigators: |
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| Project Partners: |
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| Department: |
Electronics and Computer Science |
| Organisation: |
University of Southampton |
| Scheme: |
Standard Research (Pre-FEC) |
| Starts: |
01 September 1993 |
Ends: |
28 February 1997 |
Value (£): |
243,934
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| EPSRC Research Topic Classifications: |
| Electronic Devices & Subsys. |
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| Panel History: |
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Summary on Grant Application Form |
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This EPSRC project is a three year collaboration between the Department of Electronics and Computer Science, Southampton University, the Department of Electrical and Electronic Engineering, Liverpool University and the Department of Physics, Warwick University. The aim of the project is to realise a number of novel MOS and bipolar device structures using SiGe.Progress:Two batches of heterojunction bipolar transistors have been completed using LPCVD SiGe [1], which have investigated the options for combining a low thermal budget polysilicon emitter with a heterojunction base [2]. Analysis of the electrical results is currently in progress, and is indicating that the physical behaviour of the polysilicon emitter is very sensitive to the thermal budget used for the emitter drive-in. Modelling work is being undertaken to explain this result. The design of a test mask for I2L circuits has been completed, and extensive device and circuit simulations have been undertaken using MEDICI. This work has allowed the performance of the proposed SiGe substrate-fed and surface-fed I2L circuits to be optimised, and has facilitated the specification of the device and process design for the first I2L batch.A batch of sub-micron MOS transistors is in the final stages of fabrication. The transistors have raised sources and drains to minimise 2D effects and low thermal budget plasma anodised gate oxides for compatibility with SiGe processing. Extensive device simulations have been carried out in order to investigate the concept of using SiGe in the source and drain regions of the MOS transistor to suppress latch-up. The simulations indicate that a dramatic reduction in the gain of the parasitic bipolar transistors can be achieved, and hence that latchup can be reduced [3]. A test mask for the fabrication of vertical SiGe MOS transistors is currently being designed, which will then be used to experimentally validate the latch-up suppression concept. [1] J.M Bonar, G.J. Parker, S.J. Hamel, P. Ashburn; 'LPCVD growth of SiGe for device applications'; Proc. International Conference on Materials for Microelectronics (1994). [2] G.J. Parker, P. Ashburn, J. M Bonar, H. J. Gregory, G. P. Kennedy, J. S. Hamel; 'LPCVD SiGe for heterjunction bipolar transistors'; IEE Colloquium on advanced MOS and bipolar devices, February 1995.[3] Z.Y. Wu, L J. McDaid, S. Hall; 'Reverse heterojunction engineering: a novel technique for the suppression of the parasitic bipolar transistor in deep sub-micron MOSFETs'; IEE Colloquium on advanced MOS and bipolar devices, February 1995.
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Key Findings |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Potential use in non-academic contexts |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Impacts |
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| Description |
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk |
| Summary |
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| Date Materialised |
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Sectors submitted by the Researcher |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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| Project URL: |
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| Further Information: |
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| Organisation Website: |
http://www.soton.ac.uk |