Details of Grant 

EPSRC Reference:	GR/J13830/01
Title:	AN INVESTIGATION INTO TEST STRATEGIES FOR MULTI CHIP MODULES
Principal Investigator:	Jalowiecki, Dr I
Other Investigators:	Disliss, Dr C Dislis, Dr C
Researcher Co-Investigators:
Project Partners:
Department:	Electronic & Computer Engineering
Organisation:	Brunel University London
Scheme:	Standard Research (Pre-FEC)
Starts:	01 September 1993	Ends:	29 February 1996	Value (£):	82,831
EPSRC Research Topic Classifications:	System on Chip VLSI Design
EPSRC Industrial Sector Classifications:
Related Grants:
Panel History:
Summary on Grant Application Form
To investigate and model the cost-effectiveness of test and burn-in strategies for multi-chip modules.Progress:The investigation strategy is:1) To automate a pre-existing MCM manufacturing cost-model.2) To incorporate a 'test cost estimator', to predict die and module test costs (based on easily derivable circuit metrics) for boundary scan test methodologies.3) To incorporate models for a variety of die test and burn-in strategies deployable in the die procurement phase ('Known Good Die').4) To investigate test cost estimation for non-boundary-scan methodologies.Progress achieved in the first 12 months is:1) A preliminary spreadsheet-based manufacturing economics model has been completed. 2) A 'test cost estimator' has been incorporated to predict die and module test costs based on easily derivable circuit metrics. Published in: C. Disliss, C, I.P. Jalowiecki, I.P, Test Strategies for Multi-chip Modules Based on Economics Considerations , Proceedings of the IEEE WSI Conference, San Francisco, January 1995. 3) Models for the yield and cost of various die test strategies ('Known Good Die') have been incorporated. Published in: C. Disliss, C, I.P. Jalowiecki I.P, Economics Modelling for the Determination of Optimal Known Good Die Strategies , Proceedings of the IEEE Multi Chip Module Conference, Santa Cruz, February 1995. 4) The work has also been presented at a Workshop on Known Good Die, held at Brunel in August 1994, with participants from the ITIC (Interconnection Technology Industrial Consortium). 5) Preliminary evaluation of the economics of the selected test and burn-in strategies has been carried out using cost data derived from: a. known prototype and production MCM technologiesb. TAB and die-carrier Known Good Die (KGD) test methodologiesFurther evaluations are underway, recognising the fact that cost factors are rapidly evolving in this volatile market sector.
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Organisation Website:	http://www.brunel.ac.uk