Details of Grant 

EPSRC Reference:	GR/J14530/01
Title:	BUILT IN SELF TEST FOR SWITCHED CURRENT MODE DEVICES
Principal Investigator:	Toumazou, Professor C
Other Investigators:
Researcher Co-Investigators:
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Department:	Electrical and Electronic Engineering
Organisation:	Imperial College London
Scheme:	Standard Research (Pre-FEC)
Starts:	16 September 1993	Ends:	15 September 1995	Value (£):	34,906
EPSRC Research Topic Classifications:	Design & Testing Technology
EPSRC Industrial Sector Classifications:
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Panel History:
Summary on Grant Application Form
(i) To investigate the applicability of current monitoring for unified test and diagnosis of switched current devices. (ii) To determine the practicability of designing switched mode devices to be reconfigurable to allow built-in current sensing and built-in test vector generation during test.Progress:The objectives of this project have been satisfied. The research has been conducted in collaboration with the University of Hull. The switched-current technique is an analogue discrete time signal processing technique fully compatible with digital CMOS VLSI technology. It can be regarded as a true mixed signal methodology. The feasibility of current monitoring for the unified test of switched current circuits has been demonstrated on a number of test examples via simulation. Application of classical current-monitoring techniques have highlighted the natural ability of switched-current devices to monitor faults. Novel test strategies have been applied and close to 100% fault coverage has been exemplified and this includes monitoring of simulated G.O.S. faults.In collaboration with the University of Hull we have demonstrated the concept of concurrent analogue test, we believe, for the first time. As part of the natural operation of the switched current device, the device subtlely is reconfigured into a self-testing mode during a particular clock phase. Performance of the device is not compromised during test. We have identified that this natural concurrent-test feature is pertinent to switched-current processors and offers enormous potential for future mixed-signal VLSI processors. A test chip is currently being fabricated in CMOS VLSI technology, based upon a simple switched-current integrator design, and this should clearly demonstrate the practical merits of this work. The research has this far culminated in 5 international publications and 2 book chapters.
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Organisation Website:	http://www.imperial.ac.uk