Details of Grant 

EPSRC Reference:	GR/J16701/01
Title:	A SOLUTION TO THE INTER-CHIP COMMUNICATIONS BOTTLENECK USING A FAULT TOLERANT F.D.M SYSTEM
Principal Investigator:	Curtis, Dr K
Other Investigators:	Hayes-Gill, Professor B
Researcher Co-Investigators:
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Department:	Sch of Electrical and Electronic Eng
Organisation:	University of Nottingham
Scheme:	Standard Research (Pre-FEC)
Starts:	01 May 1993	Ends:	30 April 1995	Value (£):	67,469
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Summary on Grant Application Form
1) To formalise the number of communications channels possible (packing capability) down a single wire using a Fault Tolerant F.D.M. system for analogue inter-chip communications. Simulation will be based on transfer models of on-chip filters and oscillators. Different neural network architectures will be investigated to overcome errors introduced by overlapping of filter transfer functions. 2) Repeat 1) for digital inter-chip communications with 8,16,32,64 & 128 bits.3) Carry out an initial study into the silicon area required for 1) and 2).Progress:Both of sections 1) and 2) above have been concluded, and 3) is to be concluded shortly. The first part of the work was concerned with VLSI simulations. To this end a previous design of an Operational Transconductance Amplifiers was improved. HSPICE Simulation and layout using Mentor Graphics CAD software was carried out, and small signal parameters were extracted from the layout. Distortion analysis was also performed. These parameters were used to construct and behavioural models of filter and oscillator banks. From these results the frequency packing capability was estimated. The next work carried out was investigation of neural network structures for removing cross- channel interference due to overlapping filter transfer functions in the FDM channel. This was carried out for both noiseless and noisy signals corrupted by gaussian noise, for analogue and digital waveforms. Methods of visualisation of the interference were also investigated. Neural networks architectures with various numbers of neurons and layers were trained using LMS and backpropagation algorithms. It was found that a limited connectivity architecture is able to reduce errors by orders of magnitude with the use of many fewer weights than a fully connected network. Furthermore, the model is inherently scalable. Transmission of analogue data required a linear neuron transfer function for both learning and recall, whereas digital data required a non-linear transfer function. Therefore, a neuron with variable gain transfer function is proposed as a VLSI building block. Blind source separation, using an unsupervised network, was also attempted for demultiplexing of the FDM signals. It was found that the technique worked well for a small number analogue sub-channels, but not for digital data, so for these reasons and because it relies on a fully connected architecture, this avenue was not pursued. As expected, the use of neural networks enables better frequency utilisation. Silicon area estimation using the OTA building block as a unit of measurement is in progress.
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