Details of Grant 

EPSRC Reference:	GR/J47729/01
Title:	ARCHITECTURAL SYNTHESIS OF VLSI SIGNAL PROCESSING CHIPS
Principal Investigator:	Woods, Professor RF
Other Investigators:	McCanny, Professor Sir JV
Researcher Co-Investigators:
Project Partners:
Department:	Sch of Electronics, Elec Eng & Comp Sci
Organisation:	Queen's University of Belfast
Scheme:	Standard Research (Pre-FEC)
Starts:	01 November 1993	Ends:	31 October 1996	Value (£):	129,927
EPSRC Research Topic Classifications:	Design & Testing Technology
EPSRC Industrial Sector Classifications:	Electronics
Related Grants:
Panel History:
Summary on Grant Application Form
To undertake research to extend a new architectural synthesis methodology, the Modular Design Procedure (MDP), which has been developed for the design of practically realisable DSP chips. To create a new design automation environment, IRIS, based on MDP, which will allow a non-specialist to automatically generate optimised VLSI circuit architectures from a high level algorithmic description To couple IRIS to lower level CAD tools in order to demonstrate the automated design of a DSP chip from algorithm to architecture to layout.Progress:The Modular Design Procedure has been extended to the design of recursive filters, DCT transforms, arithmetic processors, adaptive algorithms and algorithms for disk drive applications. Some interesting developments were noticed in the application of the MDP to adaptive algorithms which have lead to the Procedure being extended.Considerable progress has been achieved in the development of IRIS. The environment has been partitioned into a number of interacting subsystems which include a schematic editor, simulation and verification functions, SFG transforms, parameterized processor models interface, schematic and processor library facilities, and circuit retiming routines. The tools have been developed around a shell which allows subsystems to be easily added and the tools to be transferred between host workstations. The schematic editor has been created and allows SFG schematics to be created and a number of functions to be carried out upon them. The cell library containing models of the various parameterized processors and the user library containing previously designed schematics has also been designed along with a symbolic simulator which will generate a difference equation for the SFG under consideration. Mostly importantly, the scaling and retiming procedures have been written which determine the scaling rate and re-timing of the SFG. This system at present allows the users to develop practically realisable architectures and explore options by choosing different library components. The next phase of the work will be the development of a numerical simulator which will allow the user to assess the numerical performance of the design and algorithm optimisation programs. Considerable progress has been made in interfacing these tools to lower level CAD tools. A VHDL interface has been developed which allows the code to be transported to VHDL synthesis tools. The Compass ASIC Navigator tools have been used to successfully synthesise a first order IIR filter design based on a carry-save multiplier. This illustrates the ability of the tool to automatically produce circuit layouts from SFG descriptions of the algorithm. Several other designs including a 8 point DCT and a full second order IIR filter are presently being carried out. All layout issues such as clock distribution etc. have been addressed.
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Organisation Website:	http://www.qub.ac.uk