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Details of Grant 

EPSRC Reference: GR/K00752/01
Title: ASYNCHRONOUS DEAD AREA TEST FOR SYNTHESIZED ASICS
Principal Investigator: Brown, Professor AD
Other Investigators:
Currie, Mr A Wilkins, Dr B Zwolinski, Professor M
Researcher Co-Investigators:
Project Partners:
Pre Nexus Migration
Department: Electronics and Computer Science
Organisation: University of Southampton
Scheme: Standard Research (Pre-FEC)
Starts: 01 January 1995 Ends: 31 March 1996 Value (£): 50,216
EPSRC Research Topic Classifications:
Design & Testing Technology
EPSRC Industrial Sector Classifications:
Electronics
Related Grants:
Panel History:  
Summary on Grant Application Form
Any complex digital system, at any given time during use, has areas (modules) that are dead in that they do not contain valid data, .i.e. the data that was processed or generated by that area has been passed onto a subsequent stage, and will not be required (read) again. In a synthesised system, where the flow of data is determined explicitly by an on-chip (synthesised) controller, the question of which areas will be dead or not (and when) is clearly known in advance. We can exploit this dead time and run a test pattern (either complete or in part) through an area when it is unused. This gives the ability to continuously monitor the health of the overall system, with zero impact on the processing capability. This has obvious applications in situations where reliability and safety are of concern. There may exist systems where an area is so heavily used that it is impossible to perform any testing at a serious rate; in this case three solutions present themselves; the area may be partially tested (or tested at a lower rate), the processing of real data periodically halted to allow a more thorough test to take place, or limited local parallel redundancy introduced to eliminate the testing bottleneck .
Key Findings
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Summary
Date Materialised
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Organisation Website: http://www.soton.ac.uk