Details of Grant 

EPSRC Reference:	GR/K19921/01
Title:	ADAPTIVE DSP SIGMA DELTA ALGORITHMS AND ARCHITECTURES FOR DIGITAL COMMUNICATIONS
Principal Investigator:	Stewart, Professor R
Other Investigators:
Researcher Co-Investigators:
Project Partners:
Department:	Electronic and Electrical Engineering
Organisation:	University of Strathclyde
Scheme:	Standard Research (Pre-FEC)
Starts:	01 November 1994	Ends:	30 June 1998	Value (£):	92,641
EPSRC Research Topic Classifications:	Digital Signal Processing
EPSRC Industrial Sector Classifications:
Related Grants:
Panel History:
Summary on Grant Application Form
(1) To investigate and develop a novel class of adaptive DSP algorithms and architectures using over-sampled sigma delta single bit data streams.(2) To demonstrate the applicability, and the advantages of this arithmetic processing strategy over conventional Nyquist rate PCM, DSP.(3) To integrate the adaptive sigma delta processing strategies into standard digital data communications strategies (V series modem recommendations) using adaptive echo cancellation and adaptive decision feedback equalisers.Progress:This project has 10 key work packages. Progress to date is on scheduleWork package 1 (months 1-3) undertook a state of the art review of sigma delta devices and general oversampling strategies. This review includes most of the devices available from worldwide semiconductor companies. The conclusion of this review is that the sigma delta adaptive computation strategy being investigated in this research programme is indeed timely and of high potential interest to a wide variety of adaptive DSP applications such as echo cancellation, noise cancellation, and adaptive data equalisation using sigma delta technology for input/output. In work package 2 (months 1-6) simulations of an adaptive least mean squares (LMS) adaptive filter sampling at 64 xs the Nyquist rate have been developed. These adaptive architectures use over-sampled single bit data as inputs, and output over-sampled single bit data. Hence they can be directly interfaced to sigma delta DACs and ADCs without any interpolation or decimation filtering stages. The overall on-chip hardware for an application specific adaptive LMS is less for the sigma delta implementation, when compared to the traditional Nyquist rate PCM approach. This advantage forms one of the key areas of focus for the project. We have further developed the simulations to use single bit sigma delta data, but have PCM adaptive FIR filter weights of 16, 20 and 24 bits respectively. By increasing the number of bits, the minimum mean squared error achievable with the sigma delta adaptive LMS is comparable to the traditional Nyquist rate approach. Therefore we have been able to demonstrate that the sigma delta adaptive LMS computation strategy can achieve the same performance as the traditional Nyquist rate PCM adaptive LMS but with less chip area. Current work is investigating the stability of the sigma delta adaptive filter architectures and testing the algorithm for applications of system identification, inverse system identification and noise cancellation.
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Organisation Website:	http://www.strath.ac.uk