Details of Grant 

EPSRC Reference:	GR/K54120/01
Title:	MIXED-SIGNAL FAULT MODELLING AND SIMULATION
Principal Investigator:	Zwolinski, Professor M
Other Investigators:
Researcher Co-Investigators:
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Department:	Electronics and Computer Science
Organisation:	University of Southampton
Scheme:	Standard Research (Pre-FEC)
Starts:	14 July 1995	Ends:	13 April 1996	Value (£):	4,000
EPSRC Research Topic Classifications:	Design & Testing Technology
EPSRC Industrial Sector Classifications:
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Summary on Grant Application Form
Various techniques have been proposed for testing analogue and mixed-signal circuits. These include functional testing and power-supply current monitoring. With integrated circuits, it is not possible to insert faults into real circuits in order to assess the effectiveness of the testing methods, and it has therefore proved necessary to use simulation to model fault-free and faulty circuits and to compare their behaviours. While simulation is an effective tool for digital circuits, it has proved far too costly for analogue circuits. Typically, a 7 bit analogue to digital converter, used as an example mixed-signal circuit, can take up to 9 hours to simulate on a SPARCstation. Such a circuit has about 500 nodes and 400 transistors. Therefore to model, for instance, all the possible behaviours of the circuit if any two nodes are bridged together would take several hundred years! This king of performance is clearly unacceptable and impractical.It is proposed, therefore, that two approaches should be considered:a) Analogue behavioural modelling. In the simulation approach already tried, the various parts of the circuit are modelled at a transistor level. This gives a very accurate indication of the supply current and of the detailed functional behaviour. The complexity of the transistor models accounts for a substantial part of the computational time. If large parts of the circuit can be modelled at a higher level of abstraction, the computational effort could be significantly reduced. While behavioural models of linear analogue circuits can be produced relatively easily, non-linear models and models of effects such as non-linear supply currents are much harder to model. Indeed, it is not believed that such work has been previously undertaken.b) Novel analogue fault simulation algorithms. Conventional analogue simulation is expensive. Analogue fault simulation requires that many faulty versions of a circuit be simulated. The larger the circuit, the more likely it is that parts of that circuit exhibit the same or similar behaviour as the original fault-free circuit in the presence of a fault. Thus, is performing a fault simulation, redundant calculations are performed. Preliminary work suggests that computational savings can be made by exploiting this redundancy in novel simulation algorithms. While this approach is not within the scope of either of the existing projects, some work is needed before the idea can be developed in further research projects.
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Organisation Website:	http://www.soton.ac.uk