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Details of Grant 

EPSRC Reference: GR/L28128/01
Title: RELIABILITY DESIGN FOR ULTRA-SHORT-GATE CMOS TECHNOLOGIES
Principal Investigator: Kelsall, Professor RW
Other Investigators:
Researcher Co-Investigators:
Project Partners:
Pre Nexus Migration
Department: Electronic and Electrical Engineering
Organisation: University of Leeds
Scheme: Standard Research (Pre-FEC)
Starts: 01 September 1997 Ends: 31 August 2000 Value (£): 118,086
EPSRC Research Topic Classifications:
VLSI Design
EPSRC Industrial Sector Classifications:
Electronics
Related Grants:
Panel History:  
Summary on Grant Application Form
The silicon MOSFET is the basic 'building block' of the majority of integrated circuits, including VLSI memory chips and ASICs. The operating characteristics of a MOSFET deteriorate during its lifetime, dependent on the electrical stress experienced. Eventually, the MOSFET ceases to operate within its intended specification; this behaviour, repeated in even a small fraction of FETs in a chip, can lead to unreliability or complete failure. In short-gate device (which offer higher speeds and integration densities) the electrical stresses are greater, leading to accelerated degradation. Progress to ultra-small feature sizes in CMOS will be critically dependent on the ability to 'design out' degradation at the device level. The aims of the project are, by a combination of advanced theoretical and experimental techniques, to gain a detailed understanding of the physical mechanisms of hot-electron-induced degradation of ultra-short-gate-devices. This understanding will then be used to develop an accurate ageing simulator for ULSI CMOS design. Alternative FET gate dielectric materials will also be investigated in the quest for improved device reliability.
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Organisation Website: http://www.leeds.ac.uk