Details of Grant 

EPSRC Reference:	GR/L54356/01
Title:	METHODS AND TOOLS FOR DEVELOPING RECONFIGURABLE SERIAL DESIGNS
Principal Investigator:	Luk, Professor W
Other Investigators:
Researcher Co-Investigators:
Project Partners:
Department:	Computing
Organisation:	Imperial College London
Scheme:	Standard Research (Pre-FEC)
Starts:	01 May 1997	Ends:	31 October 2000	Value (£):	190,170
EPSRC Research Topic Classifications:	VLSI Design
EPSRC Industrial Sector Classifications:	Electronics
Related Grants:
Panel History:
Summary on Grant Application Form
The aim of this project is to develop methods and tools for producing serial hardware designs that can be reconfigured at run time. Such designs can be implemented efficiently using Field-Programmable Gate Arrays (FPGAs), now widely used in industry and academia, because they allow short design cycles, low development costs and in-situ upgrades, run-time reconfiguration and serial processing are two proven approaches to effective FPGA utilisation. Our recent work indicates that combining these approaches will offer new opportunities in optimising designs and will yield innovative solutions to problems in many important applications (such as audio processing) where the data flows are serial. For instance, reconfiguration adds flexibility to a serial data-path and combining the control circuitry for reconfiguration and serialisation will improve hardware sharing. This combined framework will cover digit-serial techniques; it should greatly enrich our recipes for re-configurable processing by supporting a wide variety of designs, from the fully-parallel to the fully serial. The project will start with the development of building blocks for re-configurable serial designs; composition strategies and compilation schemes will then be explored. Further work includes optimising the methods and the tools and extending them to cover other design styles such as on-line arithmetic or multi-rate processing.
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Organisation Website:	http://www.imperial.ac.uk