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Details of Grant 

EPSRC Reference: GR/M12223/01
Title: A NOVEL BUMPING METHOD FOR FLIP CHIP ASSEMBLY
Principal Investigator: Holmes, Professor A
Other Investigators:
Researcher Co-Investigators:
Project Partners:
Celestica Ltd Exitech Ltd
Department: Electrical and Electronic Engineering
Organisation: Imperial College London
Scheme: Standard Research (Pre-FEC)
Starts: 05 October 1998 Ends: 04 April 2000 Value (£): 93,287
EPSRC Research Topic Classifications:
Design & Testing Technology
EPSRC Industrial Sector Classifications:
Electronics
Related Grants:
Panel History:  
Summary on Grant Application Form
This project will investigate a novel flip chip bumping method for use in chip-on-board (COB) applications. The method involves: 1) fabrication of arrays of electroformed metal columns on a silica carrier with a polymer sacrificial layer; 2) array bonding of the columns to their respective chips; 3) release of the bumped chips from the carrier by excimer laser ablation (through the carrier) of the sacrificial layer. Separate bonding (thermosonic) and release stages are envisaged in the first instance. However we will also investigate the feasibility of a combined release-and-bond process in which the columns are transferred from carrier to chip in a single process step.The new bumping method is attractive to the electronics assembly industry because: 1) it requires minimal processing of the silicon wafer; 2) it is applicable to small pad geometries; 3) it is potentially a wafer-scale process; 4) it uses technologies that are already established in the industry; 5) it allows a wide range of column geometries to be explored.The proposed research is closely allied to an existing EPSRC project funded under the EPDM Programme (GR/L 61767), and the new bumping method will be evaluated in collaboration with the existing project.
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Organisation Website: http://www.imperial.ac.uk