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EPSRC Reference: GR/M51567/01
Title: TRANSLATION FROM DELAY-INSENSITIVE ALGEBRA INTO PETRI NETS,WITH APPLICATION TO ASYNCHRONOUS CIRCUIT DESIGN
Principal Investigator: Josephs, Professor MB
Other Investigators:
Researcher Co-Investigators:
Project Partners:
Department: Information Systems and Information Tech
Organisation: London South Bank University
Scheme: Standard Research (Pre-FEC)
Starts: 15 April 1999 Ends: 14 October 2000 Value (£): 46,590
EPSRC Research Topic Classifications:
VLSI Design
EPSRC Industrial Sector Classifications:
No relevance to Underpinning Sectors
Related Grants:
Panel History:  
Summary on Grant Application Form
The semiconductor industry is beginning to appreciate the opportunities (such as low power dissipation and low electro-magnetic emission) for application of asynchronous circuit technology. Exploitation will require appropraite methods and tools for be available to the digital logic designer. Currently, Petri nets (signal transition graphs) are popular for specification purposes. Asynchronous logic synthesis tools (such as Petrify) are available that take Petri nets as input.Process algebras are the main alternative to Petri nets a s a means of specifying concurrent systems. process algebras (in common wit the hardware description languages VHDL and Verilog) are textual and permit an algorithmic style of specification. DI-Algebra, in particular, is relevant to asynchronous circuti design because it supports hierarchical specification and verification of modules that communicate by delay-insensitive signalling.The proposed programme involves the development of a method and tool by which process-expressions in DI-Algebra can be automatically translated into Petri nets. The idea is that designers should;1. Specify modules using DI-Algebra,2. Translate such specifications into Petri nets using the new tool, and 3. Perform validation and circuit synthesis using existing tools.
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Organisation Website: http://www.lsbu.ac.uk