EPSRC Reference: |
GR/M93758/01 |
Title: |
MODELLING AND VERIFICATION OF INTERCONNECTS FOR SYSTEM ON-CHIP ARCHITECTURES |
Principal Investigator: |
Eder, Professor K |
Other Investigators: |
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Researcher Co-Investigators: |
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Project Partners: |
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Department: |
Computer Science |
Organisation: |
University of Bristol |
Scheme: |
Standard Research (Pre-FEC) |
Starts: |
01 March 2000 |
Ends: |
31 May 2003 |
Value (£): |
51,411
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EPSRC Research Topic Classifications: |
Microsystems |
System on Chip |
VLSI Design |
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EPSRC Industrial Sector Classifications: |
Electronics |
No relevance to Underpinning Sectors |
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Related Grants: |
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Panel History: |
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Summary on Grant Application Form |
Investigation of formal techniques that support the design of System-on-Chip (SOC) architectures, in particular on-chip interconnects. SOCs integrate a number of co-operating modules on a single chip; typically dedicated for a specific domain, e.g. multimedia processing. These modules are linked via a high-speed processing with real time communication and provide a challenging application. A variety of formal approaches to modelling, analysis and verification of general hardware and communication systems exits, their practical use of formal techniques by integrating different approaches in a uniform verification environment specialised to support SOC design. The first project stage develops a modelling framework that can be used to represent the functional behaviour of a SOC, as well as its performance analysis. The system will be tested using a formal model of a multimedia SOC. A CCS/CSP-based modelling language and techniques based on the observational behaviour paradigm are expected to be suitable.
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Key Findings |
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Potential use in non-academic contexts |
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Impacts |
Description |
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Summary |
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Date Materialised |
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Sectors submitted by the Researcher |
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Project URL: |
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Further Information: |
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Organisation Website: |
http://www.bris.ac.uk |