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EPSRC Reference: GR/N64526/01
Title: A RESOURCE-AWARE FUNCTIONAL LANGUAGE FOR HARDWARE SYNTHESIS
Principal Investigator: Mycroft, Professor A
Other Investigators:
Researcher Co-Investigators:
Project Partners:
A T & T Laboratories-Cambridge Ltd
Department: Computer Science and Technology
Organisation: University of Cambridge
Scheme: Standard Research (Pre-FEC)
Starts: 01 October 2000 Ends: 30 September 2003 Value (£): 75,014
EPSRC Research Topic Classifications:
Parallel Computing
EPSRC Industrial Sector Classifications:
Communications Electronics
Information Technologies No relevance to Underpinning Sectors
Related Grants:
Panel History:  
Summary on Grant Application Form
Current hardware synthesis languages (VHDL, Verilog) provide structural (assembly-like) and behavioural (higher-level) descriptions of hardware. They are difficult to reason about and to transform; optimisations tend to be proprietary and ad hoc.Our research is to consider functional languages as a framework for hardware specification and synthesis. Functional languages have simple transformation rules and ease the introduction of parallelism compared with non-declarative formulations.In contrast to previous work by Sheeran our use of functional languages is {resource aware}-i.e. function definitions represent functional units. Two calls to a function represent a shared functional unit (accessed by a bus or multiplexer and protected by some form of arbitration if necessary). Standard program transformations e.g. fold-unfold produce alternative mappings on the area-time spectrum. E.g. duplicating a function definition creates two similar functional units which may then be locally optimised if they are now not shared. Moreover, the functional high-level form can map into synchronous and asynchronous hardware (or even a mixture) with timing constraints being handled by automatically inserted (user-strategy not user-tactics) latches and arbiters.
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Organisation Website: http://www.cam.ac.uk