| EPSRC Reference: |
GR/R02429/01 |
| Title: |
Feasability Study: Automated Hdl Generation of Asynchronous Reconfigurable Microprocessors |
| Principal Investigator: |
Allan, Dr G |
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| Department: |
Sch of Engineering |
| Organisation: |
University of Edinburgh |
| Scheme: |
Fast Stream |
| Starts: |
01 April 2001 |
Ends: |
30 June 2002 |
Value (£): |
59,261
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Summary on Grant Application Form |
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This proposal aims to extend the use of asynchronous circuits in ICs and FPGAs by permitting the automatic generation of an asynchronous dual-rail/NCL microprocessor HDL descriptions and the associated emulator, debugger, compiler and assembler. The processor will be generated from a simple o-code based description, enabling a processor to be generated to match a particular applications requirement. This capability will be used as the basis of future research into the generation of an asynchronous microprocessor optimisation system and research into large co-operative systems optimised asynchronous processors, matched to a specific target application.
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Key Findings |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Potential use in non-academic contexts |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Impacts |
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| Description |
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk |
| Summary |
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| Date Materialised |
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Sectors submitted by the Researcher |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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| Project URL: |
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| Further Information: |
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| Organisation Website: |
http://www.ed.ac.uk |