EPSRC Reference: |
GR/R96583/01 |
Title: |
On-chip Tuning of Analogue Integrated Circuits for System-on-Chip Implementations |
Principal Investigator: |
Toumazou, Professor C |
Other Investigators: |
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Researcher Co-Investigators: |
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Project Partners: |
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Department: |
Electrical and Electronic Engineering |
Organisation: |
Imperial College London |
Scheme: |
Standard Research (Pre-FEC) |
Starts: |
01 August 2002 |
Ends: |
31 July 2005 |
Value (£): |
325,640
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EPSRC Research Topic Classifications: |
Digital Signal Processing |
System on Chip |
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EPSRC Industrial Sector Classifications: |
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Related Grants: |
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Panel History: |
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Summary on Grant Application Form |
The aim of this project is to develop strategies, algorithms and architectures to enable the on-chip tuning of analogue circuits for system-on-chip implementations. With the current industry drive towards fully-integrated system solutions, more and more analogue circuitry is being brought on-chip alongside the digital processor, logic and memory. We aim to exploit the digital circuitry to help tune and control the analogue circuitry, in order to improve yield and reduce production test times. This requires the development of new algorithms and architectures for the digital tuning of analogue circuitry. We propose to apply novel statistical techniques to solve the tuning and optimisation problems; in particular we will look at the statistical ideas of Design of Experiments (DOE) and Response Surface Methods (RSM). We have already demonstrated the effectiveness of these techniques to several areas of electronic and electrical design. Firstly, we will develop strategies and algorithms for post-manufacture tuning of analogue integrated circuits, to improve yield of system-onchip implementations. The focus here will be on the development of simple models and algorithms that enable the tuning process to be achieved in a short time and with as little computational overhead possible. The second application is the tuning/optimisation of analogue circuit parameters when taking a system-on-chip design to a new (scaled) process. The focus here will be on developing statistical methods that enable this re-optimisation to be carried out in an efficient and almost automatic manner.
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Key Findings |
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Potential use in non-academic contexts |
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Impacts |
Description |
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Summary |
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Date Materialised |
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Sectors submitted by the Researcher |
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Project URL: |
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Further Information: |
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Organisation Website: |
http://www.imperial.ac.uk |