Details of Grant 

EPSRC Reference:	GR/S96913/01
Title:	Ultrathin gate dielectrics for submicrometer polymer field -effect transistors
Principal Investigator:	Sirringhaus, Professor H
Other Investigators:
Researcher Co-Investigators:
Project Partners:	Bangor University Cornell University
Department:	Physics
Organisation:	University of Cambridge
Scheme:	Standard Research (Pre-FEC)
Starts:	01 March 2005	Ends:	29 February 2008	Value (£):	189,850
EPSRC Research Topic Classifications:	Electronic Devices & Subsys.
EPSRC Industrial Sector Classifications:	Electronics
Related Grants:	GR/S96920/01
Panel History:
Summary on Grant Application Form
Thin dielectrics are one of the key components required to realize short-channel organic transistors that satisfy fundamental scaling requirements. A high performance, ulrathin polymer dielectric is as critical for performance enhancement of organic transistors by miniaturization as ultrathin silicon dioxide has been for downscaling of silicon MOSFETs. This project is focussed on high-performance, ultrathin polymer gate dielectrics with thickness less than 50nm for printed, submicrometer polymer FETs. The project builds on recent advances in the Cavendish group on defining submicrometer and even sub-100nm critical features by direct-write printing, as well as on forming high performance polymer semiconductor-polymer dielectric interfaces by self-assembly techniques.The specific goal of the project is twofold:(I) Science - Systematic study of the correlation between structural and electronic properties of self-assembled polymer semiconductor - polymer dielectric interfaces: Systems will be used for which the interface morphology can be controlled by kinematic parameters during growth or by post-processing techniques. A detailed understanding of the dependence of electrical properties on parameters such as interface roughness and dielectric purity is crucial for advancing organic TFT device technology.(Ii) Device technology - Development of high performance gate dielectrics that allow continuous scaling of dielectric thickness from 100 nm down to 10nm for submicrometer FETs with channel lengths ranging from 1 micron to less than 100 nm. The resulting improvement in device performance and reduction of operating voltage will be demonstrated.
Key Findings
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Organisation Website:	http://www.cam.ac.uk