| EPSRC Reference: |
GR/H40075/01 |
| Title: |
PRACTICAL YIELD OPTIMISATION FOR LARGE AREA ICS USING YIELD PREDICTION AND LAYOUT ADJUSTMENT |
| Principal Investigator: |
Walton, Professor AJ |
| Other Investigators: |
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| Researcher Co-Investigators: |
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| Project Partners: |
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| Department: |
Sch of Engineering |
| Organisation: |
University of Edinburgh |
| Scheme: |
Standard Research (Pre-FEC) |
| Starts: |
01 January 1993 |
Ends: |
31 December 1995 |
Value (£): |
84,056
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| EPSRC Research Topic Classifications: |
| Design & Testing Technology |
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Summary on Grant Application Form |
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1. To develop a system that can generate IC layouts with yields comparable to handcrafted designs. 2. To develop algorithms for efficient calculation of predicted IC layout yields and recalculation after small layout systems.3. To develop algorithms to calculate the yield of systems with modular redundancy.Progress:This project has developed a software environment that takes layout generated by automated place and routing algorithms and adjusts the layout to make it more robust to defects without increasing the circuit area. This uses fast yield estimates of small layout changes to guide track sorting and displacement, bumping and net sliding. Since 50% of yield loss is typically attributed to interconnect any reduction has the potential to be significant. The actual improvement in defect sensitivity is dependent upon the original layout but greater than 10% improvements are typical. The EYE software tool has also been developed to evaluate the defect sensitivity of commercial layouts. It is based on an original O(N log N) algorithm for calculating critical area developed by the project. The algorithm uses line edges and consequently is not restricted to Manhattan layout. The software can determine the critical areas of both extra and missing material defects as well as those for pin holes. The package has the capability to calculate these critical areas hierarchically, enabling critical area estimates of even the largest designs. The EYE software tool is about to go on trial release to other researchers in this field. An O(N log N) algorithm for identifying and measuring the probability of individual circuit faults has also been developed. Faults can be classified according to the type of failure, e.g. as local, causing failure of only part of a circuit for which a replacement exists, or global, causing total circuit failure. Yield estimates for local and global fault types are combined to estimate the yield of circuits with redundant modules. This algorithm is being integrated into the EYE system. This algorithm can also be used to help improve test strategies by using it to predict the probability of individual failures.
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Key Findings |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Potential use in non-academic contexts |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Impacts |
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| Description |
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk |
| Summary |
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| Date Materialised |
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Sectors submitted by the Researcher |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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| Project URL: |
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| Further Information: |
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| Organisation Website: |
http://www.ed.ac.uk |