| EPSRC Reference: |
GR/J51214/01 |
| Title: |
NOVEL CIRCUIT TECHNIQUES FOR MONOLITHIC MICROWAVE POWER AMPLIFIERS |
| Principal Investigator: |
Robertson, Professor I |
| Other Investigators: |
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| Project Partners: |
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| Department: |
Electronic Engineering |
| Organisation: |
Kings College London |
| Scheme: |
Standard Research (Pre-FEC) |
| Starts: |
01 March 1994 |
Ends: |
29 February 1996 |
Value (£): |
74,732
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| EPSRC Research Topic Classifications: |
| RF & Microwave Technology |
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| EPSRC Industrial Sector Classifications: |
| Communications |
Electronics |
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Summary on Grant Application Form |
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The project is to investigate advanced monolithic microwave power amplifiers using novel circuit topologies and device layouts. These are being investigated at microwave frequencies using the GEC-Marconi (Caswell) foundry. The techniques to be investigated are:- Impedance-transforming power dividers/combiners, optimum device layout and placement, gate/drain manifold design, ultra-low impedance transformers using multi-level metals, and techniques for DC bias injection with unconditional stability.Progress:Ultra-low impedance transformers using multi-level metalsThe recently introduced thin-film microstrip (TFMS) technique has previously been used at Kings to realise 4-W transmission lines for a l-Watt X-band amplifier. This work has been extended to realise multilayer CPW ultra low impedance lines with lower loss and higher current handling capacity. The fabrication has been carried out at Kings as part of a separate EPSRC project on multi-layer circuit fabrication. A number of CPW test structures are ready for measurement at the time of writing. Impedance-transforming power dividers/combinersBy power combining many small devices the thermal problem and problems of matching to very low impedances are eased considerably. However, the combined size and loss of the matching networks and power dividers/combiners are a major drawback. Our solution is to employ divider/combiners that are impedance-transforming, so that they carry out the matching process inherently. This has been investigated using branch-line couplers for both the GEC-Marconi foundry process and for our own experimental multi-layer process. Optimum device layout and placementIn order to ease the thermal problems encountered with the monolithic power FET it is necessary to distribute the FET around the chip in some way. This can be done with the cluster matching technique where several smaller FETs are combined, or with novel FET layouts such as the serpentine FET. An optimum device layout has been simulated which employs a travelling wave approach. Amplifier DemonstratorsA number of demonstrators are being designed for the next GEC Marconi fabrication run (May 95). We have a number of target specifications provided by industrial contacts. One important design is a 17- 18 GHz amplifier for our indoor radio project. The next phase of the project is to investigate gate/drain manifold design using field-based simulation, and to try to improve the design of DC bias injection networks.
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Key Findings |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Potential use in non-academic contexts |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Impacts |
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| Description |
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk |
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Sectors submitted by the Researcher |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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