| EPSRC Reference: |
GR/K42073/01 |
| Title: |
APPLICATION SPECIFIC VERIFICATION TECHNIQUES FOR HIERARCHICAL ASYNCHRONOUS DIGITAL DESIGN |
| Principal Investigator: |
Barringer, Professor H |
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| Department: |
Computer Science |
| Organisation: |
Victoria University of Manchester, The |
| Scheme: |
Standard Research (Pre-FEC) |
| Starts: |
01 October 1994 |
Ends: |
31 March 1998 |
Value (£): |
248,430
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| EPSRC Research Topic Classifications: |
| Fundamentals of Computing |
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Summary on Grant Application Form |
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This project will deliver prototype verification, analysis and simulation tools for supporting hardware design engineers in high level, non-clocked, i.e. asynchronous design. The project brings together (i) various items of generic technology (process algebra framework - PAF, generic term software development package - GT, and others) developed for providing formal support in synchronous hardware design, (ii) extensive research in concurrency semantics, specification and verification, (iii) the hands-on experience of RISC processor design using Sutherland's micro pipeline philosophy. Following the approach we successfully used for the foundations of ELLA, a process algebra based semantics for an HDL with micropipeline primitives which facilitates reasoning at a higher, more natural, design level, will be developed. Specialised symbolic manipulation tools will be implemented for control and data verification, together with tools for activity, power and timing analysis. The tool development will be user-centred through close liaison with the Department's and other external hardware designers.
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Key Findings |
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Potential use in non-academic contexts |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Impacts |
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| Description |
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| Summary |
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| Date Materialised |
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Sectors submitted by the Researcher |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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