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Details of Grant 

EPSRC Reference: GR/L14664/01
Title: YIELD PREDICTION AND DFM OF IC LAYOUT
Principal Investigator: Walton, Professor AJ
Other Investigators:
Researcher Co-Investigators:
Project Partners:
Pre Nexus Migration Zarlink
Department: Sch of Engineering
Organisation: University of Edinburgh
Scheme: Standard Research (Pre-FEC)
Starts: 01 April 1996 Ends: 30 September 1999 Value (£): 210,112
EPSRC Research Topic Classifications:
VLSI Design
EPSRC Industrial Sector Classifications:
Electronics
Related Grants:
Panel History:  
Summary on Grant Application Form
The project will exploit the lead that the EYE software tool gives the UK in Critical Area (CA) extraction of IC layout. It will concentrate on increasing the accuracy and speed of hierarchical CA extraction to enable the routine use on even the largest IC devices. In addition a methodology will be developed for the cost effective generation and collection of process defectivity data to enable yield prediction to the required accuracy. CA extraction will also be used to classify the manufacturability of existing library cells as well as highlighting regions and parts of an IC layout that can be made more robust to defects. It is proposed that IC layout that can be made more robust to defects. It is proposed that IC devices will be fabricated to verify the predicted enhancements resulting from the use of the EYE tool. An interactive version of the extraction tool will be developed to enable designers easy access to layout defect sensitivity visualisations. The research will increase competitiveness of the UK IC industry by providing accurate cost estimates of new products and enabling cost benefit analysis of a range of layout and process yield enhancement strategies.
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Organisation Website: http://www.ed.ac.uk