EPSRC Reference: |
GR/L28531/01 |
Title: |
THE POST-STRESS DEGRADATION OF MOS DEVICES |
Principal Investigator: |
Zhang, Professor JF |
Other Investigators: |
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Researcher Co-Investigators: |
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Project Partners: |
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Department: |
Engineering Tech and Maritime Operations |
Organisation: |
Liverpool John Moores University |
Scheme: |
Standard Research (Pre-FEC) |
Starts: |
01 December 1997 |
Ends: |
31 May 2001 |
Value (£): |
104,542
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EPSRC Research Topic Classifications: |
Electronic Devices & Subsys. |
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EPSRC Industrial Sector Classifications: |
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Related Grants: |
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Panel History: |
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Summary on Grant Application Form |
The stress induced device degradation is one of the main factors limiting the operation voltage and speed of MOS circuits. Degradation can occur not only during the stress, but also after the stress is terminated. There is little information available on the post-stress degradation and the current understanding of it is poor. The aim of this research proposal is to carry out a systematic investigation on the post-stress degradation. It will start with establishing the dependence of post-stress degradation on key experimental parameters, such as temperature and electrical field strength. Efforts will then be made to model the dynamic behaviour of the post-stress degradation. The physical mechanism will be studied and the origin of the instability will be explored. Based on the above information, the impact of post-stress degradation on device lifetime will be assessed. The whole programme will be carried out in collaboration with industry and research centres, which are developing advanced CMOS processes.
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Key Findings |
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Potential use in non-academic contexts |
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Impacts |
Description |
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Summary |
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Date Materialised |
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Sectors submitted by the Researcher |
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Project URL: |
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Further Information: |
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Organisation Website: |
http://www.livjm.ac.uk |