| EPSRC Reference: |
GR/L42957/01 |
| Title: |
NEW SILICON ON INSULATOR (SOI) HIGH VOLTAGE DEVICES |
| Principal Investigator: |
Milne, Professor WI |
| Other Investigators: |
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| Department: |
Engineering |
| Organisation: |
University of Cambridge |
| Scheme: |
Standard Research (Pre-FEC) |
| Starts: |
07 July 1997 |
Ends: |
28 February 1998 |
Value (£): |
219,731
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| EPSRC Research Topic Classifications: |
| Electronic Devices & Subsys. |
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| EPSRC Industrial Sector Classifications: |
| No relevance to Underpinning Sectors |
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Summary on Grant Application Form |
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A new SOI (Silicon on Insulator) technology for power devices and power integrated circuits is proposed. The new technology is based on partial oxide isolation with interrupted oxide and p+ buried layers. The new soi technology improves significantly the breakdown capability, temperature behaviour and latch-up immunity of the power cells with no compromise in the switching speed or on-state resistance. Moreover, the low power cells (e.g. low voltage MOSFETs) are completely isolated as in the standard SOI technology to remove parasitic electrical interferences. The new technology is expected to play a major role in the new generation of power-integrated circuits.
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Key Findings |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Potential use in non-academic contexts |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Impacts |
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| Description |
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk |
| Summary |
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| Date Materialised |
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Sectors submitted by the Researcher |
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This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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| Project URL: |
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| Further Information: |
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| Organisation Website: |
http://www.cam.ac.uk |