EPSRC Reference: |
GR/M93741/01 |
Title: |
0.03UM VERTICAL SHALLOW TRENCH CMOS TECHNOLOGY (VST-CMOS) |
Principal Investigator: |
Hall, Professor S |
Other Investigators: |
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Researcher Co-Investigators: |
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Project Partners: |
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Department: |
Electrical Engineering and Electronics |
Organisation: |
University of Liverpool |
Scheme: |
Standard Research (Pre-FEC) |
Starts: |
04 September 2000 |
Ends: |
03 June 2004 |
Value (£): |
262,210
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EPSRC Research Topic Classifications: |
Electronic Devices & Subsys. |
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EPSRC Industrial Sector Classifications: |
Electronics |
No relevance to Underpinning Sectors |
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Related Grants: |
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Panel History: |
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Summary on Grant Application Form |
This project investigates a novel method of producing vertical MOSFETs with nanometer (0.03micron) channel lengths using a combination of epitaxy and shallow trench isolation. Alternative vertical MOS transistor architectures are investigated by simulation and fabrication, including single gate, double gate and gate-all-round structures incorporating the silicon on insulator concept. Processing modules relevant to the vertical transistor will be researched, specifically; realisation of a 5nm trench gate oxide technology with some regard to reliability; methods for reducing gate overlap capacitance; methods for maximising transistor current drive; methods of optimising the epitaxy and shallow trench isolation. The gate oxide work will emply advanced oxide characterisation techniques and the establishment of new techniques of value to UK and European industry.
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Key Findings |
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Potential use in non-academic contexts |
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Impacts |
Description |
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Summary |
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Date Materialised |
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Sectors submitted by the Researcher |
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
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Project URL: |
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Further Information: |
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Organisation Website: |
http://www.liv.ac.uk |