| EPSRC Reference: |
GR/R32895/01 |
| Title: |
COmputational HEteRogEneously timed NeTworks (COHERENT) |
| Principal Investigator: |
Davies, Professor AC |
| Other Investigators: |
|
| Researcher Co-Investigators: |
|
| Project Partners: |
|
| Department: |
Electronic Engineering |
| Organisation: |
Kings College London |
| Scheme: |
Standard Research (Pre-FEC) |
| Starts: |
01 July 2001 |
Ends: |
30 September 2001 |
Value (£): |
264,262
|
| EPSRC Research Topic Classifications: |
| Energy Efficiency |
System on Chip |
| VLSI Design |
|
|
| EPSRC Industrial Sector Classifications: |
| Aerospace, Defence and Marine |
Communications |
| Electronics |
Transport Systems and Vehicles |
|
| Related Grants: |
|
| Panel History: |
| Panel Date | Panel Name | Outcome |
|
13 Feb 2001
|
Electronics, Comms & Functional Materials
|
Deferred
|
|
|
Summary on Grant Application Form |
|
COHERENT proposes to construct embedded real-time systems of medium complexity as on-chip systems (SoCs) with heterogeneous timing in order to improve timing and energy efficiency of systems for portable and miniature applications in control, robotics, image processing etc. The proposed concept of a hardware-oriented architecture for such systems, called real-time networks on chip (RTNoC), will consist of computational units of maximum diversity (outside the scope of the project) and communication components from a (finite set) of generic asynchronous communication mechanisms (ACMs), which is the focus of this project. The project will deliver a design methodology for RTNoC together with a parametrised library of ACM IP blocks that will, in the longer term, allow the designer to map an application-oriented specification of the system to its implementation with maximum transparency and minimum loss of time and energy resources. It will bridge the gap between the existing (e.g. MASCOT) ideas of building distributed real-time systems and those of globally asynchronous-locally synchronous (GALS) for SoCs by investigating techniques for efficient hardware implementation of the elements of communication and multitasking support in the former, and providing a wide range of asynchrony levels, from fully synchronous to wait-free and maximally non-blocking, for the latter. This will enable the seemless composition of systems with time-driven and data-driven parts.
|
|
Key Findings |
|
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
|
|
Potential use in non-academic contexts |
|
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
|
|
Impacts |
|
| Description |
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk |
| Summary |
|
| Date Materialised |
|
|
|
|
Sectors submitted by the Researcher |
|
This information can now be found on Gateway to Research (GtR) http://gtr.rcuk.ac.uk
|
| Project URL: |
|
| Further Information: |
|
| Organisation Website: |
|